Honored Contributoron page 2.17 of the UG, it states: replace the endpoint application layer with your own design.
I expected to find a module with the Avalon MM signals, where I can connect my design, I spend hours to browse through the files, but did not find the appropriate module, Has anybody a hint for me ?? Thanks
Honored ContributorWhich user guide? My copy of the PCI Express Compiler User Guide doesn't have a gage 2.17. The advice I've been getting is to use SOPC Builder and put the PCIe interface in there. This lets you connect to Avalon-MM devices.
Honored ContributorIP Compiler for PCI Express
User Guide Document last updated for Altera Complete Design Suite version: Document publication date: 11.0 May 2011 I run SOPC, again a lot of files (100), but I am not even able to determine which the top level module is.Honored ContributorI found it:
in hip_s4gx_gen1x8_qsys_tb_hip_s4gx_gen1x8_qsys_inst.v signals like bar1_0_address, or bar1_0_writedata are the Avalon MM signalsHonored ContributorIf you take a look at the Qsys design,
http://www/support/refdesigns/ip/interface/ref-pciexpress-ddr3-sdram.html It is easy to understand. You just need to connect your own design in the Qsys. The example only has few blocks, so it will help you understand more. You can chose either connecting your logic to bar or the DMA.
