Forum Discussion
3 Replies
- Altera_Forum
Honored Contributor
They all create a DC fifo that work identically (its the same code underneath). But you cannot simulate 2). Avoid BDF editor like the plague.
- Altera_Forum
Honored Contributor
Here's what I found to answer my question:
http://www.altera.com/support/kdb/solutions/rd08152003_8247.html?gsa_pos=19&wt.oss_r=1&wt.oss=dcfifo - Altera_Forum
Honored Contributor
1) Generates a DCFIFO component with a "basic" interface, to be used directly in VHDL/HDL code.
2) Does the the same as 1 and generates a component to be used in BDF. 3) Generated a DCFIFO component with an Avalon-ST interface, to be used as part of a Qsys system. So, you use 3) when you need a DCFIFO in a Qsys system 2) when you need a DCFIFO for a piece of logic you're creating using BDF. And you should avoid BDF at all if possible. 1) when you need a DCFIFO for a piece of logic you're creating using VHDL/Verilog.