Altera_Forum
Honored Contributor
15 years agoVIP, Parallel processing
We have a working design as follows:
CVI -> CSC -> DEI -> FB -> Scaler -> CR -> Interlacer -> CVO This works fine for video up to 1080P input/output. The VIP is run at 160MHz. Now we are trying to get larger images down the pipe - 2560 x 1600 @ 60Hz so the pixel clock is 268.5MHz. I've tried to run the VIP at 260 - 270MHz but the part just won't run that fast (Stratix III EP3SE80F780C3). The Deinterlacer will run up to about 210MHz. The Frame Buffer and Scaler seem to max out at about 245MHz. I've checked this with TimingGen and trial and error with live video. I'm tasked with trying to split the image into two pieces and run a duplicate path to process both halves and then piece them back together. I'm curious if anyone has attempted to do this or if anyone may have advice on how to do it. I think I can add a component to SOPC to monitor (for example) the output Vsyncs and add backpressure via "din_ready" to do some alignment. Our concern is since I'll have two Frame Buffers performing drop/repeat for frame rate conversion and I have to share memory between the two paths that there may become a Frame delay between the two paths. Not sure how to handle this. Any input would be appreciated.