VIP FrameBuffer - How do you think it is accessing the SDRAM?

Whether the memory controller supports bursts to the memory or not, performing bursts on the Avalon bus will increase the efficiency.

With SDRAM, there are extra delays whenever you change addresses or change from read to write. If you perform small random reads or writes, the effective data rate will be much less than your memory clock speed.

For example, writing and reading 10 words each alternating between read and write will be much slower than writing 10 words consecutively followed by reading 10 words consecutively.

Using bursts on your avalon master port will ensure more consecutive access to memory. Another way that might work is to change the arbitration shares in SOPC builder and use pipelined access.