VIP FrameBuffer - How do you think it is accessing the SDRAM?

Hi Kevin, your comments are very helpfull and I got it now working, also I still don't understand how it is possible to compute the pixeldata in time for the altera framebuffer.

I have attached a sketch how the FB is right now attached to my system. In the settings of the FB I set 128bit for the Port width and 256 as burst target. I still don't understand, what the sopc build from this information. In my opinion it should not be possible to buffer the incoming data to write and read it in the SDRAM with the same rate.

The SDRAM Controller is set to the same values as in my version of the system with my self build FrameBuffer. So Altera must have another trick to buffer the data, that I don't found, yet. You know what I mean? I am almost doing the same thing, except the processing with 128bit word with, so I am still loosing this datarate. The problem I am getting before the datawidth problem is to access the SDRAM Controller with read and write at the same time. Perhaps they optimize the read/write some way, blockwise processing or something like that? I would love to get my FB running the same way the Altera FB does, but everything I get are fifo overflows out of it.

Thanks again for your great help.