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Altera_Forum
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16 years ago

VIP Control is Mutilating my Image!!!

Hello All, I have an interesting problem. I've managed to put together a video processing path: cvi->scaler->frame buf->cvo Which works reasonably well scaling SXGA to SVGA for displa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi Gareth,

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Do you mean the hsync input to the Clocked Video Input? The Scaler doesn't have an hsync input.

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Yes, sorry - the CVI hsync input. I will have to re-check, as I only compared the length of the hsync pulse during the vblank period. Looking from outside the FPGA, the hsync period is consistent during vblank and non-vblank.

The changes are very very useful, and definately worth-while, I'm currently relying on polling the TVP7002 to detect a change in resolution, but with the new system it would be simpler. Being a know bug, do you know if this will be addressed in a future service pack?

Thanks for helping me out, it's great to have a good community to rely on.