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Altera_Forum's avatar
Altera_Forum
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16 years ago

VIP Control is Mutilating my Image!!!

Hello All, I have an interesting problem. I've managed to put together a video processing path: cvi->scaler->frame buf->cvo Which works reasonably well scaling SXGA to SVGA for displa...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The frame buffer will write 4 pixels at a time. In other words, yes it performs efficient accesses. So right now I believe your pixels are 12 bits wide correct? The frame buffer would perform 5 pixels per transfer at 75MHz whereas right now you're only getting 2 at 150MHz. So you get 25% more pixels per access by using the half-rate controller. Again the tradeoff is the memory interface is twice as wide which means you use twice as many RAM blocks in the frame buffers for the FIFOs and your logic utilization will increase.

Also, your burst size of 256 seems excessive and can actually cause you problems in some cases. You don't want to starve the reader or writer because you've allocated too much time to each one.

Jake