VIP Clocked Video Input Seperate Sync Timing Tolerance

Hello All,

- I'm running analog video to a TI TVP7002, which decodes it into 24 bit digital clocked video with seperate syncs. My output is a vanilla parallel TTL interface SVGA LCD. Plan is to use the FPGA SOPC for scaling and filtering.

- All hooked up to the EP3C25 on the Cyclone III starter board, thorugh a Bitec breakout board, all connectivity verified

- Video inputs are ADC'd then enter the FPGA, then into a Clocked Video Input block, generated through the SOPC builder. This is where my problems start; nothing seems to get through the clocked video input.

Observations:

1) If I connect the signals straight through the FPGA to my LCD target with no processing by the VIP or other logic: The system works, I see the video signal from the generator hardware

2) If in the SOPC I use: test pattern gen --> clocked video output , I see a perfect test pattern

3) If in the SOPC I use: test pattern gen --> frame buffer (DDR) --> clocked video output, I see a perfect test pattern

4) Any time I try to use the Clocked Video Input, nothing works.

Notes:

1) All sync signals are +ve polarity (HS, VS, DE)

2) The clock is clean

3) Input Signal Timings (After ADC by TVP7002):

Pclk 50MHz

HS 47KHz

VS 75Hz

HS width 32 pixels

HBP 47 pixels

HFP 2 pixels

VS width 0 lines, 3 pixels

VBP 0 LINES, 65 pixels

VFP 0 Lines, 18 pixels

4) Analog side is a vanilla VESA 800x600 75Hz signal

5) Clocked Video Input is setup:

Vid in and Vid out do NOT use same clock (50Mhz input pclk, VIP on 200Mhz)

Seperate Sync Selected

Control port is disabled

Questions:

1) Are there any restrictions on the video signal that the Clocked video INput will accept? What Porch settings, sync widths will it take? There's no mention of these in the literature.

2) What frequency does the Clocked Video INput need to be driven at to read the incoming video - 1x the PCLK? 2x the PCLK? 4x??

3) There is mention of the Clocked Video Input block being turned 'off' by default in the literature. Is this only when the Control Port is enabled? Will it always work without the control port?

4) In general there is no mention of the clock ratios needed in the SOPC blocks, are they all single cycle blocks? Where can I find this literature?

Thanks in advance for all your help guys...

Brent from Sydney, Australia.