Honored Contributor
Honored Contributorvideo data comes out as a single bus rather than broken out as R, G, and G signals. you need to port map the 24 bit bus into your 3 components
horizontal and vertical sync aren't present because you have selected NTSC which uses synchronization signals embedded in the video data. in the Clocked Video Output you need to select sync on separate wires. i imagine dclk is the input clock vid_clk to your Clocked Video Output. you need to look up the timing signals associated with your desired video standard to fill into the Clocked Video Output.
