Video Clocked output and VGA

with a clocked input of 27MHz in CVI, and a 25MHz in CVo, which should be system clock, sdram clocks and avalon masters clocks?

I've tryied many solutions but no one seems to work..

and STILL, I don't want to use the nios..

I would start with NTSC.

The DE2 "TV Box" demonstration is working only in NTSC.

I would run it first, see it working.

Then with out turning off the board run your project (change it to NTSC).

Godluck!

Reuven

well, I think I've understand what's the problem.

I think clok settings i made are correct, but they are correct for video streams with the same frame input/output rate.

pal is 50 (760*288) frame/second, so (after clipping the imageas 640*240) the deinterlacer would output one frame for each field, so i will obtain 50 (640*480) frames as output.

But VGA output I need is 60hz, it means that i need 10 frame second.

And I suppose I have no other choice to use the Nios to enable the frame rate conversion.

Isn't it?

once last consideration: if i use NTSC as input, my system should work properly.

Am I right?

RA2M, thanks a lot for you help.

Hi,

The easiest thing to do if you suspect that frame rate is the issue would be to configure the frame buffer (or deinterlacer) as a triple buffer to handle frame rate conversion and guarantee that you will not starve the CVO or overflow the CVI. You do not need to use the Nios (at least for that).

Depending on how you parameterized it, the deinterlacer may either double the rate (input field rate = output frame rate) or maintain it (input frame rate = output frame rate) or do the frame rate conversion if it is parameterized as a triple buffer.

One more question came in my head right now..

Underflow and owerflow outputs, should be connected to anything?

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The VIP Test Pattern Generator and the clocked video output will do the work.

The only thing is that you need to connect the Clocked video output signals to the VGA HS and VS of the VGA connector and the data, blank and sync to the D2A on the DE2 board. you can use one of the video example designs that are avalible on this forum.

Goodluck,

Reuven Aboudi

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hi there,

newbie here..

sorry, i dont quite understand what you mean by this sentence :

"the only thing is that you need to connect the clocked video output signals to the vga hs and vs of the vga connector and the data, blank and sync to the d2a on the de2 board."

from the generated component i only have these pins

underflow_from_the_clk_vid_out,

vid_clk_to_the_clk_vid_out,

vid_data_from_the_clk_vid_out,

vid_datavalid_from_the_clk_vid_out,

vid_f_from_the_clk_vid_out,

vid_h_from_the_clk_vid_out,

vid_h_sync_from_the_clk_vid_out,

vid_v_from_the_clk_vid_out,

vid_v_sync_from_the_clk_vid_out

the VGA on DE2 has this pins:

output oVGA_CLOCK; // VGA Clock

output oVGA_HS; // VGA H_SYNC

output oVGA_VS; // VGA V_SYNC

output oVGA_BLANK_N; // VGA BLANK

output oVGA_SYNC_N; // VGA SYNC

output [9:0] oVGA_R; // VGA Red[9:0]

output [9:0] oVGA_G; // VGA Green[9:0]

output [9:0] oVGA_B; // VGA Blue[9:0]

which pins i should connect to oVGA_BLANK_N & oVGA_SYNC_N

what vid_v, vid_h & vid_f , underflow & datavalid from Video Clocked Output (VCO) is for ?

should i connected them to somewhere? and what is "D2A" you did mention above?

thanks..im sory for my question, it just confuse me a little

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underflow_from_the_clk_vid_out,

vid_clk_to_the_clk_vid_out,

vid_data_from_the_clk_vid_out,

vid_datavalid_from_the_clk_vid_out,

vid_f_from_the_clk_vid_out,

vid_h_from_the_clk_vid_out,

vid_h_sync_from_the_clk_vid_out,

vid_v_from_the_clk_vid_out,

vid_v_sync_from_the_clk_vid_out

the VGA on DE2 has this pins:

output oVGA_CLOCK; // VGA Clock

output oVGA_HS; // VGA H_SYNC

output oVGA_VS; // VGA V_SYNC

output oVGA_BLANK_N; // VGA BLANK

output oVGA_SYNC_N; // VGA SYNC

output [9:0] oVGA_R; // VGA Red[9:0]

output [9:0] oVGA_G; // VGA Green[9:0]

output [9:0] oVGA_B; // VGA Blue[9:0]

which pins i should connect to oVGA_BLANK_N & oVGA_SYNC_N

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I've assigned VGA_blank to vid_datavalid, vga_sync_N pulled to gnd (or vcc, i don't remeber exactly) and vga it sholud work properly.

One thing tht i've learnj until now workin in quartus2 and sopc builder is that not all the outputs from the schematic should connect to something.

Now, another question.

I thougth my video problems could come from unsufficent bandwidth, so i've set the clipper to clip a 320*240 portion of the 720*576 input.

and i've downsampled the color planes form 8bits per color plane to 5 bits per color plane, so i'll have 15 bit per pixel in RGB.

DE2 has a SDR SDRAM, whose controller works properly only at 50Mhz. So, sdram clock and sdram controller clock works both at 50Mhz.

Data width of the sdram is 16 bits, so

16bits*50mhz=800mb/s

Am I right?

using a framebuffer with triple buffering, i should have 3 buffers, so 6 avalon buses. tre buffers means that i must have at least 320*240(video heigth and width)*2 (write and read)*50hz(pal interlaced frequency)*3(numeber of buffers)= 345600000b/s as transfer rate.

So, my bandwidth should be correct.

For the framebuffer, I've set

avalon mm masters port width 64

write only masters interface FIFO depth 64

write only master interface burst depth 32

read only masters interface FIFO depth 64

read only master interface burst depth 32

I am not using pipeline rigth now..

I'ìve tryed other values, but they don't seems to work properly.

I think this should be "the problem" in my system pipeline.

and the deinterlacer i am using doesn't use buffering, only performs bob duplication. Or should I set fifos for cvi and cvo to any particular values in order to have a working system?

Could you give me any other hint, please?

Best regards

Phate

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I've assigned VGA_blank to vid_datavalid, vga_sync_N pulled to gnd (or vcc, i don't remeber exactly) and vga it sholud work properly.

One thing tht i've learnj until now workin in quartus2 and sopc builder is that not all the outputs from the schematic should connect to something.

--- Quote End ---

it works,

i hook the oVGA_SYNC to 1

learn sumting new today..thankS~

hi again..

im adding a frame buffer to my previous system

testpattern --> clocked video output (CVO)

so rite now it would be:

testpattern --> framebuffer(connected to SDRAM) --> CVO

here is my system as seen in SOPC builder

https://www.alteraforum.com/forum/attachment.php?attachmentid=2400

is the connection right?

How about the components? is it enough with just adding framebuffer?

should i add frameread component? but framebuffer does have output pin on it