Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

VHDL-Code with Avalon Bus Interface-/ and VHDL-Video-System-Interface-Ports

Hello I provided the following ENTITY. Can I actually provide a IP, which some haven connectivity with the Avalon bus, as well as haven as down descriptive for the VHDL_Detector, which is not c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

you need an avs_address, avs_read, avs_write signals. Your address will be however many spots you need, which sounds like only 1, so it can be a std_logic rather than a std_logic_vector. Then when the avs_write is strobed you look at the address to see who you are writing to. Same for the read. your reg.h file is generally correct, but can be simplified: 


# define IORD_IME_AVALONE_XY_DETECTOR_DATA() IORD(XY_DETECTOR_BASE,0)
# define IOWR_IME_AVALONE_XY_DETECTOR_DATA(data) IOWR(XY_DETECTOR_BASE,0, (data))
# define IORD_IME_AVALONE_XY_DETECTOR_CONTROL() IORD(XY_DETECTOR_BASE,1)
# define IOWR_IME_AVALONE_XY_DETECTOR_CONTROL(data) IOWR(XY_DETECTOR_BASE,1, (data))

Not sure if you want 1 or 4 for the offset of the second one. I have never really used the IO_CALC_ADDRESS_NATIVE functions as I always use 32-bit slaves with 32-bit masters, so the offset is always 4.

Help?

Kevin