Verilog: tri-state mux

Hello,

This is obviously a beginner question, but I am getting some odd behavior from a tri-state mux, and was just wondering if someone could check the correctness of this code:

inout [7:0] bus;

wire bus_oe;

wire select;

wire [7:0] data1;

wire [7:0] data2;

assign bus = bus_oe ? (select ? data1:data2): 8'hZZ;

The behavior sought is: if 'bus_oe' is false then 'bus' is HiZ, otherwise if 'select' is true connect 'bus' to 'data1', if false connect 'bus' to 'data2'.

I am using Quartus II 10.0 with a cyclone II chip.

Thanks,

Wahran