using DSPs in the FPGA as ALMs for standard FFT IP

downloaded the 18.1 but the actual task not tried yet because the project in 16.1 i was using for some other task, as soon as it finish i will try this and update you here. Sorry for the delay.

Hi,

The following is the picture of resource of the example project i have created and it's simulation results. You can see mine for the same configuration consuming only 2k ALMs and no DSPs.

Even the simulation in Modelsim using that also not getting proper results. In my main project also around same 2k resources it's consuming and the result there i am seeing in signal tap and even that project result also from source output all are zeros except the dc bin with some amplitude. I am not getting to know where the problem is happening with this fpga part and why no results producing properly.

To see the simulation in the mentor folder run fftblock.do in modelsim so that you can see the result too. But , whole problem is same that now it's is confirmed for me that my fft ip somehow inside signals getting trimmed whether it is 16.1 or 18.1 even for a sample code and not consuming any dsp and not giving any result.

Please help me in this aspect what is the problem of my project or my settings. By the way I am doing 2048 fft don't get confused with 4096 name and example project you gave also changed to 2048 fft and the resource consumption table shown in last picture.

Hi, I tried this 18.1 folder keeping in 16.1 installation as you suggested.

The following is the resource consumption table after synthesis of the example project attached by you previously. You can see FFT with DSP consumes around 4k ALMS and 18 DSPs

Hi,

The issue is solved now. THe whole problem is because of the Twiddle factor width which is given as 24 and datawidth given as 16 and for this configuration your fft ip will not synthesize propely where as when i gave both as 16 bit and then checked things are working in both simulation and implementation and it is consuming dsps also without giving any attribute itself.

But all this confusion started as you see because for the above mentioned wrong configuration simulation in model sim still working.

and to answer you questions.

1) does the design able to simulate using your testbench for Q16.1 fft?

--> Yes it is able to simulate in model sim for Q16.1 itself.

2) Also, I notice that your resource had drop for your FFT. In your screenshot, it show it had about 10000++ ALUT but your design only shows 2097. This means that you have leave your pin float. You cannot leave your pin float as it will optimized a way a lot of logic.

--> It's not dropping because of floating pin etc, it is because of the above twiddle problem with your fft ip as i mentioned it's trimming the multiplier logic itself in synthesis. and 10K for you consuming may be because when you open project the ip of fft taking defualt varibale streaming config instead of what i configured for so once open qsys of ip and regenerate and run.

3) Can you make your design when tools -> simulation tools -> rtl simulation works? from my side, if I do that, I see error messages.

--> I didnt do simulation directly as you can see some file called fftblock.do in my zip folder in mentor folder, that i am running as macro file in modelsim.

4) if your design work for Q16.1fft, can you attached it for me to make comparison as well? I will try it on Q18.1 to see if this can be work or not.

--> The problem is not with 16.1 at all it is config problem of fft.

5) you do not need to zip the whole design to send it as it take a lot of spaces. Just project -> archive project and it would be sufficient. please resend your design after you make the changes above.

--> this i am aware of but sent you zip to give you the essence of all the background generated files and to find any mistake in it if possible and to pass you simulation code of model sim also.

Hence, the problem solved. The twiddle factor related thing actually explained to us today by one of our local field application engineer.