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jjang
New Contributor
New ContributorUsing Altera PLL make 500Khz or below
When i Using ALTPLL, i Usually make 500khz and below xx kHz Frequency Clock. @ 50Mhz / 100Mhz Input clock. But Cyclone 5, Different PLL IP Core. - ALTPLL → Altera PLL, so it doesn't support fo...
Hi,
just read PLL Intel FPGA IP messages thoroughly. It instructs you to enable physical output clock pararameters to configure cascaded output counters.
jjangNew Contributor
New ContributorAs Clocking and PLL User Guide..
Using PLL Clock (C1, C2. C3.C4), then that can though Global clock.
but to make a Clock as a Logic (such as Counter).. will not connect to Global clock . .isn't it?
FvM
Super Contributor
Super ContributorHi,
just read PLL Intel FPGA IP messages thoroughly. It instructs you to enable physical output clock pararameters to configure cascaded output counters.
