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Altera_Forum
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10 years ago

Using Altera PCI AV-MM DMA IP with custom MSI interrupts

I am researching the necessary elements to create a new design to transfer data from a FPGA based device to a host computer using PCI-e interface. So long, i have looked into the PCI-e Avalon-MM DMA ...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Hi Guys,

Anyone is successful in generating interrupts using Mailbox registers?

If yes, please provide the procedure and the interrupt generation flow.

Iam referring to this UG: https://www.altera.com/en_us/pdfs/literature/ug/ug_a10_pcie_avmm.pdf

My design uses Arria-10 FPGA Avalon-MM with DMA but with external DMA descriptor controller.

I have used the below BARs in the Qsys design:

BAR0 -> RD/WR Descriptor Contoller Slave

BAR2 -> CRA Slave

BAR4 -> On-chip Memory slave

I would like to know how to write into Avalon-MM to PCI Express Mailbox Registers (0x3A00–0x3A1F) and PCI Express-to-Avalon-MM Mailbox Registers (0x0800–0x081F) ?

Is it through Host Software application or by using any other component in the design?

Regards

linus_alt