Using Altera PCI AV-MM DMA IP with custom MSI interrupts

Hi tanjomar,

You interpreted document correctly.Altera PCIe IP Core supports MSI/MSI-x interrupt.But it doesn't include logic to store address and data required for MSI/MSI-x interrupt.You can find it from the altera wiki.Following is the link.

http://www.alterawiki.com/wiki/handling_pcie_interrupts

You just need to instantiate pci_irq in Qsys/SOPC design.I don't have much idea about MSI interrupt but I know it supports up to 4 MSI-x interrupt.Source code is available so you can expand it for more number of interrupt.

Regards,

Krupesh

Hi guys,

Tanjomar did you manage to implement this with the Cyclone V PCIe Avalon-MM DMA reference design?

Krupesh, you mention above that this can be achieved by instantiating the pci_irq block from the design in the link you shared in Qsys. This design (http://www.alterawiki.com/wiki/handling_pcie_interrupts) is for Stratix V and the PCIe HIP used is pci_sv_hip_avmm, the reference design I am working with for the Cyclone V uses the pci_256_hip_avmm - an690: PCIe Avalon-MM DMA - does this matter?

I can identify two potential issues with instantiating the pci_irq block in the DMA reference design:

First, the irq_gen_master interface from the pci_irq block connects to Txs, I presume this is how the interrupts are sent upstream (?), however in the DMA reference design this port is already driven by read /write descriptor controller masters to send memory read /writes to the pcie domain, as well as the descriptor controller sending the DMA done MSI. Could this port maintain this functionality in addition to handling a custom MSI?

Second is the BAR resources available, in the Stratix V design they are utilized as follows (each bar is 32-bit non-prefetchable memory):

BAR2 -> Cra (pcie_sv_hip_avmm)

BAR3 -> MSIX_Structure_Slave (pci_irq)

BAR4 -> Irq_source_slave (irq_srource(x))

In the DMA reference design BAR0 (64-bit prefetchable memory) is internally connected to the descriptor controller and BAR4 (32-bit non-prefetchable) connects to the on-chip memory. This still leaves BARs 2/3/5 available as 32-bit non-prefetchable to be connected as BARs 2/3/4 are in the Stratix MSI design however I am not sure if this will actually work.

I do not fully understand what is being achieved by the BAR2 -> Cra and BAR4 -> Irq_source_slave connections in the Stratix V MSI design. Regarding the former I have read the the PCI HIP Cra interface must be connected to use interrupts but why is this? Regarding the latter the output of each of the irq_source blocks is only 1 bit (signifying an interrupt) which connects to the interrupt_receiver interface of the pci_irq block, why are the irq_source_slave ports of the irq_source blocks driven by BAR4?

My goal is to be able to generate a custom interrupt in relation to some event such as memory becoming full and send this to the host side where a user-space app. can act accordingly. Perhaps there is a more straightforward way of doing this?

Any help around any of these questions would be greatly appreciated.

Regards,

Aidan

The mechanism to generate interrupt in Avalon-MM PCIe DMA IP is same as the Avalon-MM 64/128bit Hard IP (non-DMA) when this IP is configured properly for sending the required interrupt.

However, Avalon-MM PCIe DMA IP version doesn't expose the RxmIrq port, users might need to use Mailbox to generate MSI interrupt.

Writing A2P_Mailbox to send MSI to far-end with the AvMM DMA PCIe IP.

(This message was posted on behalf of Intel Corporation)

Hi Guys,

Anyone is successful in generating interrupts using Mailbox registers?

If yes, please provide the procedure and the interrupt generation flow.

Iam referring to this UG: https://www.altera.com/en_us/pdfs/literature/ug/ug_a10_pcie_avmm.pdf

My design uses Arria-10 FPGA Avalon-MM with DMA but with external DMA descriptor controller.

I have used the below BARs in the Qsys design:

BAR0 -> RD/WR Descriptor Contoller Slave

BAR2 -> CRA Slave

BAR4 -> On-chip Memory slave

I would like to know how to write into Avalon-MM to PCI Express Mailbox Registers (0x3A00–0x3A1F) and PCI Express-to-Avalon-MM Mailbox Registers (0x0800–0x081F) ?

Is it through Host Software application or by using any other component in the design?

Regards

linus_alt