Using Altera PCI AV-MM DMA IP with custom MSI interrupts

Hi guys,

Tanjomar did you manage to implement this with the Cyclone V PCIe Avalon-MM DMA reference design?

Krupesh, you mention above that this can be achieved by instantiating the pci_irq block from the design in the link you shared in Qsys. This design (http://www.alterawiki.com/wiki/handling_pcie_interrupts) is for Stratix V and the PCIe HIP used is pci_sv_hip_avmm, the reference design I am working with for the Cyclone V uses the pci_256_hip_avmm - an690: PCIe Avalon-MM DMA - does this matter?

I can identify two potential issues with instantiating the pci_irq block in the DMA reference design:

First, the irq_gen_master interface from the pci_irq block connects to Txs, I presume this is how the interrupts are sent upstream (?), however in the DMA reference design this port is already driven by read /write descriptor controller masters to send memory read /writes to the pcie domain, as well as the descriptor controller sending the DMA done MSI. Could this port maintain this functionality in addition to handling a custom MSI?

Second is the BAR resources available, in the Stratix V design they are utilized as follows (each bar is 32-bit non-prefetchable memory):

BAR2 -> Cra (pcie_sv_hip_avmm)

BAR3 -> MSIX_Structure_Slave (pci_irq)

BAR4 -> Irq_source_slave (irq_srource(x))

In the DMA reference design BAR0 (64-bit prefetchable memory) is internally connected to the descriptor controller and BAR4 (32-bit non-prefetchable) connects to the on-chip memory. This still leaves BARs 2/3/5 available as 32-bit non-prefetchable to be connected as BARs 2/3/4 are in the Stratix MSI design however I am not sure if this will actually work.

I do not fully understand what is being achieved by the BAR2 -> Cra and BAR4 -> Irq_source_slave connections in the Stratix V MSI design. Regarding the former I have read the the PCI HIP Cra interface must be connected to use interrupts but why is this? Regarding the latter the output of each of the irq_source blocks is only 1 bit (signifying an interrupt) which connects to the interrupt_receiver interface of the pci_irq block, why are the irq_source_slave ports of the irq_source blocks driven by BAR4?

My goal is to be able to generate a custom interrupt in relation to some event such as memory becoming full and send this to the host side where a user-space app. can act accordingly. Perhaps there is a more straightforward way of doing this?

Any help around any of these questions would be greatly appreciated.

Regards,

Aidan