UniPhy DDR3 IP Instantiation in Custom Top-Level HDL Module

Hello,

I have a problem with uniphy DDR3 IP instantiation.

If I use IP core's top-level hdl module (I mean, ddr write/read controller is inside the IP core's top-level) then DDR3 works.

But if I create a new hdl module and use it as a top-level, instantiate IP core in this new top-level module then first read data always is 0xAAAAAAAA and it is wrong.

Do I need to do something special to use uniphy ddr3 IP core in my custom top-level like some modifications in pin_assignments.tcl/timing.tcl tcl files?

Thank you,

Ali