Forum Discussion

Honored Contributor

11 years ago

UniPhy DDR3 IP Instantiation in Custom Top-Level HDL Module

Hello, I have a problem with uniphy DDR3 IP instantiation. If I use IP core's top-level hdl module (I mean, ddr write/read controller is inside the IP core's top-level) then DDR3 wor...

Altera_Forum

Honored Contributor

11 years ago

By the way, it can be useful following informations:

- Quartus version: Quartus II 64 Bit, 14.1.0 Build 186

- Target Device: Arria V GX Starter Kit (http://www.altera.com/products/devkits/altera/kit-arria-v-starter.html)

- DDR3 SDRAM Controller with UniPHY version 14.1

Forum Discussion

UniPhy DDR3 IP Instantiation in Custom Top-Level HDL Module

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