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JuanEscobedo's avatar
JuanEscobedo
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4 months ago

Unexpected behavior of DDR3 controller on Arria V GZ when using manual refresh

deHello, I am using the DDR3 controller IP on an Arria V GZ FPGA and I am noticing a different behavior when issuing a refresh request using the manual refresh interface. When issuing the refresh a...
Memory
AdzimZM_Altera's avatar
AdzimZM_Altera
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4 months ago

Hi Juan Escobedo,


I'm Adzim from Altera. I will assist you in this forum.


Is there activation signal that you are controlling when running the test?


Is it having any temperature dependency for the readatavalid to toggle suddenly?


Can you try without burst mode or burst of 8 transactions?


Regards,

Adzim


JuanEscobedo's avatar
JuanEscobedo
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4 months ago

Hello Adzim,

Thank you for your help with this issue. Sorry it took me a bit to circle back to this project.

Can you clarify what you mean with activation signal? I hold everything in reset (DDR controller and state machines), and when I release it, everything just starts. The first thing all state machines check if the DDR controller ready signal is asserted. If it is, then we proceed with the read/write operations.

I doubt temperature is an issue but I am unsure how to check that.

About burst mode, we have another design that is simpler: just reads and writes the same burst length to the same address, then increments address, and repeats that works fine:

Each read/write cycle is 341 clock cycles and the refresh signal is sent every 3 of the read/write cycles (1023 clocks total). Could there be an issue with the timing of my refresh signal?

I also noticed in the working old design the ready signal does get de-asserted for 1 clock cycle after a write.

I can work on changing the control logic to have bursts of 8.

Juan