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Occasional ContributorTX sync header error insertion in Arria 10 GX
Hi,
I have a problem regarding Tx error insertion function on Arria 10 GX 10GBASE-R with FEC.
I have built two duplex 10GBASE-R with FEC PHYs on my board, connecting Tx to Rx through DAC cable.
Packet Transmit and receive test is working good by viewing Rx stream port by Signal Tap.
For error insertion test, I have set "Enable TX sync header error insertion" option in the parameter editor, and I drove the tx_err_ins PHY input port.
But I have no Rx stream change after error insertion.
In my thought, by receiving corrupted sync header in the RX, the rx_enh_blk_lock output port would go low.
Do you have any method to confirm sync header error was inserted in the TX encoder?
In another point, I have unclear description in the user guide:
Table 24. 64b/66b Encoder and Decoder Parameters on Page 60,
---
"Enable TX sync header error insertion"
When you turn on this option, the Enhanced PCS supports cycleaccurate error creation to assist in exercising error condition testing on the receiver.
When error insertion is enabled and the error flag is set, the encoding sync header for the current word is generated incorrectly.
If the correct sync header is 2'b01 (control type), 2'b00 is encoded. If the correct sync header is 2'b10 (data type), 2'b11 is encoded.
---
I can't find what "the error flag" is.
Thank you for any help.
20 Replies
MamaSaruzying,
I am sorry that I totally don't understand your explanation.
I will try to make my question more clear.From description of Table 24, Two conditions should be realized to insert sync header error:
1. error insertion is enabled
I am very clear that this condition is realized by setting "Enable TX sync header error insertion" GUI check box on.
2. the error flag is set
I mean what is the error flag?Regards,
MamaSaru
ZiYing_IntelFrequent Contributor
Hi MamaSaru,
After some discussion with our team, the error flag in the user guide maybe means "rising edge of C.0x089 bit[5] setting (0->1)."
Best regards,
zying
- MamaSaru
Hi,
By reading the section 6.19 of the user guide, It said that rewriting individual register is not recommended.Besides, I have investigated where "Enable TX sync header error insertion" GUI setting contribute to the register map by comparing generated files under setting on and off.
I compared below files:
altera_xcvr_native_a10_reconfig_parameters.h
altera_xcvr_native_a10_reconfig_parameters.mif
altera_xcvr_native_a10_reconfig_parameters.svI have found that "Enable TX sync header error insertion" GUI setting contributes to "C.0x089 bit[5]".
According to your answer, "the error flag" comes from register "C.0x089 bit[5]" for condition 2 and "error insertion is enabled" also comes from register "C.0x089 bit[5]" for condition 1.
This explanation is not regal.I think that the AND gate should be located output of the register "C.0x089 bit[5]".
I attached the rough drawing.Regards,
- ZiYing_Intel
Hi MamaSaru,
For further information, you may refer to its block diagram. Hope the attached image was useful to you.
Best regards,
zying
- MamaSaru
zying,
I understand the current inplementation of header error insertion function.
My intention is modification request to drive exposed signal like tx_err_ins for error insertion without using individual register modification.
This makes this function usable and match with current explanation on the user guide (two condition needed for insertion).
Please tell development team my request.
regards,
MamaSaru
- ZiYing_Intel
Hi MamaSaru,
Sorry to tell you that we can't simply do modification on your design since we do not know your design requirement.
But according to your feedback, I have tell your request to development team for the enhancement design purpose. For the purpose of to drive exposed signal like tx_err_ins for error insertion without using individual register modification. This makes this function usable and match with current explanation on the user guide (two condition needed for insertion).
Best regards,
zying
- ZiYing_Intel
Hi MamaSaru,
I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.
Best regards,
zying
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