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MamaSaru's avatar
MamaSaru
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

TX sync header error insertion in Arria 10 GX

Hi, I have a problem regarding Tx error insertion function on Arria 10 GX 10GBASE-R with FEC. I have built two duplex 10GBASE-R with FEC PHYs on my board, connecting Tx to Rx through DAC cable. Pa...
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ZiYing_Intel's avatar
ZiYing_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi MamaSaru,

For further information, you may refer to its block diagram. Hope the attached image was useful to you.

Best regards,

zying

  • MamaSaru's avatar
    MamaSaru
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    zying,
    I understand the current inplementation of header error insertion function.
    My intention is modification request to drive exposed signal like tx_err_ins for error insertion without using individual register modification.
    This makes this function usable and match with current explanation on the user guide (two condition needed for insertion).
    Please tell development team my request.
    regards,
    MamaSaru