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MamaSaru's avatar
MamaSaru
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

TX sync header error insertion in Arria 10 GX

Hi, I have a problem regarding Tx error insertion function on Arria 10 GX 10GBASE-R with FEC. I have built two duplex 10GBASE-R with FEC PHYs on my board, connecting Tx to Rx through DAC cable. Pa...
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MamaSaru's avatar
MamaSaru
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hi,

By reading the section 6.19 of the user guide, It said that rewriting individual register is not recommended.

Besides, I have investigated where "Enable TX sync header error insertion" GUI setting contribute to the register map by comparing generated files under setting on and off.

I compared below files:
altera_xcvr_native_a10_reconfig_parameters.h
altera_xcvr_native_a10_reconfig_parameters.mif
altera_xcvr_native_a10_reconfig_parameters.sv

I have found that "Enable TX sync header error insertion" GUI setting contributes to "C.0x089 bit[5]".

According to your answer, "the error flag" comes from register "C.0x089 bit[5]" for condition 2 and "error insertion is enabled" also comes from register "C.0x089 bit[5]" for condition 1.
This explanation is not regal.

I think that the AND gate should be located output of the register "C.0x089 bit[5]".
I attached the rough drawing.

Regards,