Occasional ContributorTX sync header error insertion in Arria 10 GX
Hi,
I have a problem regarding Tx error insertion function on Arria 10 GX 10GBASE-R with FEC.
I have built two duplex 10GBASE-R with FEC PHYs on my board, connecting Tx to Rx through DAC cable.
Packet Transmit and receive test is working good by viewing Rx stream port by Signal Tap.
For error insertion test, I have set "Enable TX sync header error insertion" option in the parameter editor, and I drove the tx_err_ins PHY input port.
But I have no Rx stream change after error insertion.
In my thought, by receiving corrupted sync header in the RX, the rx_enh_blk_lock output port would go low.
Do you have any method to confirm sync header error was inserted in the TX encoder?
In another point, I have unclear description in the user guide:
Table 24. 64b/66b Encoder and Decoder Parameters on Page 60,
---
"Enable TX sync header error insertion"
When you turn on this option, the Enhanced PCS supports cycleaccurate error creation to assist in exercising error condition testing on the receiver.
When error insertion is enabled and the error flag is set, the encoding sync header for the current word is generated incorrectly.
If the correct sync header is 2'b01 (control type), 2'b00 is encoded. If the correct sync header is 2'b10 (data type), 2'b11 is encoded.
---
I can't find what "the error flag" is.
Thank you for any help.
.png){kind=link}