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Altera_Forum
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14 years ago

TSEMAC SW reset bit never cleared CIII+KSZ9021GQ

Hi!

I have my board with CYCIII + 2 PHY KSZ9021GQ.

During debugging web_server under NIOS i have error out

"TSEMAC SW reset bit never cleared!".

And correspondingly does not start web-server (no web-server in browser).

Who encountered a similar error?

Log start:

InterNiche Portable TCP/IP, v3.1

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.

prep_tse_mac 0

Your Ethernet MAC address is 11:22:33:44:55:66

Static IP Address is 192.168.3.250

prepped 1 interface, initializing...

[tse_mac_init]

INFO : TSE MAC 0 found at address 0x04002000

INFO : PHY Micrel KSZ9021GQ found at PHY address 0x1f of MAC Group[0]

INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0]

INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...

INFO : PHY[0.0] - Auto-Negotiation PASSED

INFO : PHY[0.0] - Checking link...

INFO : PHY[0.0] - Link established

INFO : PHY[0.0] - Speed = 100, Duplex = Full

TSEMAC SW reset bit never cleared!

OK, x=10002, CMD_CONFIG=0x00002000

MAC post-initialization: CMD_CONFIG=0x04000200

[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created

mctest init called

IP address of et1 : 192.168.3.250

Created "Inet main" task (Prio: 2)

Created "clock tick" task (Prio: 3)

Created "web server" task (Prio: 4)

Web Server starting up :(

Signals on MII - input to TSE:

https://www.alteraforum.com/forum/attachment.php?attachmentid=5148

Signals on TSE - output from FIFO of TSE:

RX

https://www.alteraforum.com/forum/attachment.php?attachmentid=5149

TX

https://www.alteraforum.com/forum/attachment.php?attachmentid=5150

19 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Are You sure You're reading the correct registers?

    Also I see that signaltap shows reset signal down, which indicates, that the system has hardware reset, rather than software reset.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    Are You sure You're reading the correct registers?

    Also I see that signaltap shows reset signal down, which indicates, that the system has hardware reset, rather than software reset.

    --- Quote End ---

    In Triple Speed Ethernet User Guide.pdf:

    https://www.alteraforum.com/forum/attachment.php?attachmentid=5152

    What is logical level for this signal in TSE 0 or 1?

    Reset in qsys

    https://www.alteraforum.com/forum/attachment.php?attachmentid=5154

    This signal from pin with pull-up resistor.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Oh, I thought this reset is not for the TSE core, but for the chip itself. The chip has reset_n pin. I don't have 9021GQ, but on 9021GN it's pin 56, which has to be pulled high. Check it's state with scope.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    Oh, I thought this reset is not for the TSE core, but for the chip itself. The chip has reset_n pin. I don't have 9021GQ, but on 9021GN it's pin 56, which has to be pulled high. Check it's state with scope.

    --- Quote End ---

    I am check reset signal on chip.

    The reset_n signal for 9021GQ is pin 110 - it always in 1 and it pulled high in my schematic.

    Led Link100 and RX on 9021GQ is active - chip not in reset.

    schematic in attachment

    https://www.alteraforum.com/forum/attachment.php?attachmentid=5155
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Something wrong with the attachments, but anyway, the problem is somewhere in the software then. You should read out PHY registers and check for real values, because the driver could possibly read wrong values if the setup is not correct.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    It seems that your tx_clk isn't toggling. What interface do you have between the MAC and the PHY? Is it regular MII?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    It seems that your tx_clk isn't toggling. What interface do you have between the MAC and the PHY? Is it regular MII?

    --- Quote End ---

    Probably that's because he use the same clk as sampling clock in signaltap.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    It seems that your tx_clk isn't toggling. What interface do you have between the MAC and the PHY? Is it regular MII?

    --- Quote End ---

    I have MII interface between PHY and MAC.