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Altera_Forum
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14 years ago

TSEMAC SW reset bit never cleared CIII+KSZ9021GQ

Hi! I have my board with CYCIII + 2 PHY KSZ9021GQ. During debugging web_server under NIOS i have error out "TSEMAC SW reset bit never cleared!". And correspondingly does not start web...
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Altera_Forum
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14 years ago

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Are You sure You're reading the correct registers?

Also I see that signaltap shows reset signal down, which indicates, that the system has hardware reset, rather than software reset.

--- Quote End ---

In Triple Speed Ethernet User Guide.pdf:

https://www.alteraforum.com/forum/attachment.php?attachmentid=5152

What is logical level for this signal in TSE 0 or 1?

Reset in qsys

https://www.alteraforum.com/forum/attachment.php?attachmentid=5154

This signal from pin with pull-up resistor.