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Altera_Forum
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14 years ago

TSEMAC SW reset bit never cleared CIII+KSZ9021GQ

Hi! I have my board with CYCIII + 2 PHY KSZ9021GQ. During debugging web_server under NIOS i have error out "TSEMAC SW reset bit never cleared!". And correspondingly does not start web...
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Altera_Forum
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14 years ago

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It seems that your tx_clk isn't toggling. What interface do you have between the MAC and the PHY? Is it regular MII?

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Probably that's because he use the same clk as sampling clock in signaltap.