FPGA programming before XCVR's ref clock is ready

Hi,

I use F-Tile Agilex 7 and Q24.2.

On power cycle (P.C) my reference transceivers clock is not ready and stable, so I do the following reset sequence to the System PLL (created for no stable XCVR's ref clock, attached):

1. When P.C, setting the refclock_ready, en_refclk_fgt_0, en_refclk_fgt_1 to 3'd0, 1'b0, 1'b0, respectively.
2. Stabling the transceiver's input reference clock (loading its config parameters)
3. Setting refclock_ready, en_refclk_fgt_0, en_refclk_fgt_1 to 3'd1, 1'b1, 1'b1, respectively.
4. Then, waiting until refclock_status, refclk_fgt_enabled_0/1 and sys_pll_locked are asserted to 1'b1

Sometimes (not often), one of the statuses on section 4 are not asserted HIGH, and thus I need to do the reset sequence again and since it fails again and again I need to do P.C again.

Is there a problem with my reset sequence?  Is there a way not to P.C the FPGA and fixing this online?

Should I synchronize between the assertion of refclock_ready, en_refclk_fgt_0 and en_refclk_fgt_1?

Thanks a lot,

Arik