TSE with SGMII in Cyclone IV GX - ALTGX_RECONFIG problem

Ok, I'm confused with this. I built a Qsys system with CPU, TSE with SGMII and some Flash/SSRAM on a Tristate bus. This all seems fine, and I can make it compile if I remove the TSE or reconfigure it with RGMII, but with SGMII using the GXB transceiver it brings out 4 reconfig signals:

reconfig_clk : IN STD_LOGIC;

reconfig_togxb : IN STD_LOGIC_VECTOR (3 DOWNTO 0);

reconfig_busy : IN STD_LOGIC;

reconfig_fromgxb : OUT STD_LOGIC_VECTOR (16 DOWNTO 0);

but if I generate an ALTGX_RECONFIG block (from ug_ethernet.pdf):

For designs targeting devices other than Stratix V and

Arria V, Altera recommends that you instantiate the

ALTGX_RECONFIG megafunction and connect the

megafunction to the dynamic reconfiguration signals to

enable offset cancellation.

I get the following signals:

reconfig_clk : IN STD_LOGIC ;

reconfig_data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);

reconfig_fromgxb : IN STD_LOGIC_VECTOR (4 DOWNTO 0);

write_all : IN STD_LOGIC ;

busy : OUT STD_LOGIC ;

channel_reconfig_done : OUT STD_LOGIC ;

reconfig_address_out : OUT STD_LOGIC_VECTOR (5 DOWNTO 0);

reconfig_togxb : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)

so where does "reconfig_data" come from? Why is "reconfig_fromgxb" 5 bits wide on the reconfig block, but 17 bits wide on the TSE? How do I hook the two together to make it compile (because if I don't connect them it moans that it needs to be connected to a DPRIO block to work)?

I have worked with DPRIO and ALTGX reconfig blocks with SDI video and there the bus widths match, the SDI megacore generates a .MIF file for the reconfig data, etc.

Any clues greatly appreciated. There don't seem to be any reference designs using SGMII!

Cheers,

Simon