Forum Discussion
Honored Contributortse_mac with dp83848 phy in MII interface
Hi
I am trying to make a design with a triple speed ethernet MAC from Altera work. I am using a National DP83848 PHY and the small 10/100 version of the MAC.Currently I have this problem: when I run the nichestack init, I get this output: InterNiche Portable TCP/IP, v3.1 Copyright 1996-2008 by InterNiche Technologies. All rights reserved. prep_tse_mac 0 prepped 1 interface, initializing... [tse_mac_init] INFO : TSE MAC 0 found at address 0x00000400 INFO : PHY National DP83848C found at PHY address 0x1f of MAC Group[0] INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0] INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... INFO : PHY[0.0] - Auto-Negotiation PASSED INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... INFO : PHY[0.0] - Auto-Negotiation PASSED INFO : PHY[0.0] - Checking link... INFO : PHY[0.0] - Link established INFO : PHY[0.0] - Speed = 100, Duplex = Half OK, x=0, CMD_CONFIG=0x01000000 MAC post-initialization: CMD_CONFIG=0x05000603 [tse_sgdma_read_init] RX descriptor chain desc (1 depth) created IP address of et1 : 0.0.0.0 Created "Inet main" task (Prio: 2) Created "clock tick" task (Prio: 3) DHCP timed out, going back to default IP address(es) Simple Socket Server starting up at the same time DP83848 is very hot? Could someone give me the golden tip to get this running?I would really appreciate your reply!14 Replies
Altera_ForumActually you're printout is exactly as it should be. I don't see anything amiss at all.
Jake- Altera_Forum
Other than your DHCP timeout. Is it supposed to be getting the IP address via DHCP (you have it connected to a DHCP server)?
You might consider changing the static IP address from 0.0.0.0 to something useful. Jake - Altera_Forum
hi jakobjones
i have connected to a dhcp server and once i change a useful ip(e.g 192.168.1.102) i get the following out: InterNiche Portable TCP/IP, v3.1 Copyright 1996-2008 by InterNiche Technologies. All rights reserved. prep_tse_mac 0 prepped 1 interface, initializing... [tse_mac_init] INFO : TSE MAC 0 found at address 0x00000400 INFO : PHY National DP83848C found at PHY address 0x1f of MAC Group[0] INFO : PHY[0.0] - Automatically mapped to tse_mac_device[0] INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... INFO : PHY[0.0] - Auto-Negotiation PASSED INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link... INFO : PHY[0.0] - Auto-Negotiation PASSED INFO : PHY[0.0] - Checking link... INFO : PHY[0.0] - Link established INFO : PHY[0.0] - Speed = 100, Duplex = Half OK, x=0, CMD_CONFIG=0x01000000 MAC post-initialization: CMD_CONFIG=0x05000603 [tse_sgdma_read_init] RX descriptor chain desc (1 depth) created IP address of et1 : 0.1.1.102 Created "Inet main" task (Prio: 2) Created "clock tick" task (Prio: 3) DHCP timed out, going back to default IP address(es) Simple Socket Server starting up - Altera_Forum
#define IPADDR0 192# define IPADDR1 168# define IPADDR2 1# define IPADDR3 102# define GWADDR0 192# define GWADDR1 168# define GWADDR2 1# define GWADDR3 1# define MSKADDR0 255# define MSKADDR1 255# define MSKADDR2 255# define MSKADDR3 0
- Altera_Forum
this " IP address of et1 : 0.1.1.102" why is it different from what i defined?
- Altera_Forum
There is a bug in the macro that converts the defines to an IP address. I think some parenthesis are missing. There is a thread about that in the Nios forum.
- Altera_Forum
hi Daixiwen
thank you very much.i almost spent two weeks to solve this problem.i expect my system can receive and transmit data packets.what should i do next?thanks again! - Altera_Forum
hi
yesterday i can ping my board(cyclone III EP3C10+SRAM+FLASH+PHY),but now it always show "request timed out ". - Altera_Forum
You should install something like Wireshark on your PC to see what is sent and received on the Ethernet link. Then use some SignalTap probes on the MII interface to see if the packets are correctly sent/received.
- Altera_Forum
Hi Daixiwen
I still can not ping my board(which I designed on my own). Pin assignment is also distrubution of my own.I'm a student and this is my first time use FPGA.can you help me check it ?please
