TSE_MAC and Timing Constraints

Hi Guys,

I'm using 2x DE2-115s with my own Ethernet design (RGMII) and i'm suspecting i'm getting timing issues. I have no real idea on how to set up constraints and i'm just trying to patch something together and i need some help.

I'm trying to follow the instructions in the TSE_MAC manual (see attached).

In short:

• ANything i do to the SDC file gets overwritten on compile.

• The manual says edit the TCL file aswell but i can't see what you would edit there.

The TSE manual (page 28, see attached screenie) discusses the generated sdc file and how you have to rename signals.

The default being:

 #  *************************************************************#  Customer modifiable constraints, value is set default by constraints#  *************************************************************#  Hierarchical path to the TSE
set SYSTEM_PATH_PREFIX ""#  Frequency of network-side interface clocks or reference clocks
set TSE_CLOCK_FREQUENCY "125 MHz"#  Frequency of FIFO data interface clocks
set FIFO_CLOCK_FREQUENCY "100 MHz"#  Frequency of control and status interface clock
set DEFAULT_SYSTEM_CLOCK_SPEED "66 MHz" #  Name the clocks that will be coming into the tse core named changed from top level 
set TX_CLK "tx_clk" 
set RX_CLK "rx_clk" 
set CLK "clk"
set FF_TX_CLK "ff_tx_clk"
set FF_RX_CLK "ff_rx_clk"
set TBI_TX_CLK "tbi_tx_clk"
set TBI_RX_CLK "tbi_rx_clk"
set REF_CLK "ref_clk"

If i change the SDC it just gets overwitten. how do i set these up correctly?

below is the details of my design we many need to know.

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I am feeding my TSE_MAC with botha firmware data path and a Nios datapath through MUX and DeMUX

My Nios is running at 100Mhz.

As pictured my TSE_MAC is running all 3 clocks at 50MHz.