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Altera_Forum
Honored Contributor
Honored ContributorTSE_MAC and Timing Constraints
Hi Guys, I'm using 2x DE2-115s with my own Ethernet design (RGMII) and i'm suspecting i'm getting timing issues. I have no real idea on how to set up constraints and i'm just trying to patch s...
Altera_ForumHonored Contributor
Honored ContributorHi guys,
I've same problem with my device (DE2-115) cyclone IV E, the relevant solutions not totally working like TSE timing constrain http://www.alterawiki.com/wiki/altera_triple-speed_ethernet_timing_contraints_design_example I still have timequest problem and the reason is ucsonstrained input paths reached to 88.
