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Altera_Forum
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15 years ago

TSE 1000BASE-X/SGMII PCS only w/LVDS I/O

Hey Guys,

I know this has been discussed a few times, but I couldn't find the answer I was looking for. I'm using a Stratix IV GX board with the Marvell Phy. I have a stripped down version of a MAC that is working on a Stratix III board using the GMII interface.. We're now trying to use the SGMII interface (ON the IV) with the PCS and PMA (I'm assuming this to be the case when I use the transceiver block with LVDS i/o - please correct me if I'm mistaken). We have a separate MDIO interface and I can read and set the Registers in the PHY (which is AN disabled, Speed 1g, Transmit Enable and SGMII (default).

I have the PCS setup as AN disabled, SGMII and Speed 1G (IF_MODE = 0x09)

The PCS Control Register is ( full Duplex, 1G) (Control = 0x140)

The PCS Status Register is ( Extened Capability, LINK_STATUS, AN ABILITY) (STATUS = 0x09) - not sure why link_status is set - but this doesn't seem to change..

So my problem is nothing seems to pass through the pcs - and I've been floundering for a couple of weeks trying to figure out why.. Any HINTS?

Fyi - I inherited all this - so I'm learning as I'm going..

Thanks Much,

Elmer.

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  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    This might seem obvious but it bit me in the rump, Do you have a valid license for the TSE? - Seems the thirty day trial expires as soon as it's not tethered.. Elmer.

    --- Quote End ---

    I use evaluation version ... I presume everythign would be okay except the fact the it will not work after sometime.

    I tried enable the bit in IF_MODE and restart negotiation, no hope.

    I took the example design, same TSE MAC settings. I do nothing, just boot up and read the partner ability register, it's all right... 0xd801 which means ... GigE mode, copper link is up ... etc ... The IF_MODE register is still 0 though. Without any writing.

    Very weird.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    I use evaluation version ... I presume everythign would be okay except the fact the it will not work after sometime.

    I tried enable the bit in IF_MODE and restart negotiation, no hope.

    I took the example design, same TSE MAC settings. I do nothing, just boot up and read the partner ability register, it's all right... 0xd801 which means ... GigE mode, copper link is up ... etc ... The IF_MODE register is still 0 though. Without any writing.

    Very weird.

    --- Quote End ---

    I deleted everything and started all over again. It worked.

    I had to change the "Loopback" option to "No loopback". The default is loopback when i first instantiate the TSE Core.

    Very weird!
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    is the 88e1111 marvell phy programmable through hardware or need software?

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Does anyone know how to config the Marvell phy? Does the TSE MAC automatically configs it through the MDIO interface, or I need to access the PHY registers (starting address 0x280)?

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The TSE won't do anything automatically. You have to access the PHY registers yourself through the MAC to configure the PHY.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks Daixiwen

    How do I know how to configure the PHY registers? I didn't find a spec of the Marvell phy that contains the registers map.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    The Marvell datasheet isn't public. You need to contact Marvell and sign an NDA to get it.

    Alternatively you can have a look at Altera's driver for the Niche stack and see what registers they configure there.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks again!

    Do you know to what address space the Marvell PHY is connected to in the Stratix IV GX development board?

    From the TSE spec I understand that if I use PCS/PMA, addresses 0x200-0x220 are allocated to the PCS.

    So I assume the PHY is connected to MDIO1, and it's address space in the MAC registers starts at 0x280. But when I try to read from this address space, it looks like I'm not reaching the PHY's registers.

    I tried to play with the definition of MDIO_ADDR1 (register 0x40 in the MAC), without a success.

    Any idea how is the PHY connected to the FPGA?

    Zoe
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You need to write the PHY address in the MDIO_ADDR1 register before you can access the registers themselves. You have 3 ways to find out which address the PHY is using:[list][*]look at the schematic and check the connections to the PHY chip that hard wire the address[*]try all the addresses from 0x00 to 0x1f until you get a response (this is what the Interniche driver does)[*]run a design example with a Nios CPU and the Interniche stack, and look for the address in the console output[/list]