TSE 1000BASE-X/SGMII PCS only w/LVDS I/O

Thanks again!

Do you know to what address space the Marvell PHY is connected to in the Stratix IV GX development board?

From the TSE spec I understand that if I use PCS/PMA, addresses 0x200-0x220 are allocated to the PCS.

So I assume the PHY is connected to MDIO1, and it's address space in the MAC registers starts at 0x280. But when I try to read from this address space, it looks like I'm not reaching the PHY's registers.

I tried to play with the definition of MDIO_ADDR1 (register 0x40 in the MAC), without a success.

Any idea how is the PHY connected to the FPGA?

Zoe