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Altera_Forum's avatar
Altera_Forum
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16 years ago

TSE + MARVELL + INICHE What am I missing???

Hi,

Can any of you see if i have done something stupid below:

I cannot transmit anyhing.

First my setup code:

alt_tse_phy_profile MV88E1116R = {"Marvell 88E1116R", //

MV88E1111_OUI, // OUI

0x24, // Vender Model Number

0, // Model Revision Number

0x11, // Location of Status Register

14, // Location of Speed Status

13, // Location of Duplex Status

10, // Location of Link Status

&marvell_phy_cfg // Function pointer to configure Marvell PHY

};

alt_tse_phy_add_profile(&MV88E1116R);

alt_tse_system_mac sys_mac = {TSE_SYSTEM_MAC(TRIPLE_SPEED_ETHERNET_0)};

alt_tse_system_sgdma sys_sgdma = {TSE_SYSTEM_SGDMA(SGDMA_ETH_TX, SGDMA_ETH_RX)};

alt_tse_system_desc_mem sys_mem = {TSE_SYSTEM_DESC_MEM(RAM_DESCRIPTOR)};

alt_tse_system_shared_fifo sys_sfifo = {TSE_SYSTEM_NO_SHARED_FIFO()};

alt_tse_system_phy sys_phy = {TSE_SYSTEM_PHY(1, NULL)};

alt_tse_system_add_sys(&sys_mac, &sys_sgdma, &sys_mem, &sys_sfifo, &sys_phy );

And console............:

Copyright 1996-2008 by InterNiche Technologies. All rights reserved.

prep_tse_mac 0

Created "Inet main" task (Prio: 2)

Your Ethernet MAC address is 01:01:20:00:00:00

prepped 1 interface, initializing...

Created "clock tick" task (Prio: 3)

[tse_mac_init]

INFO : TSE MAC 0 found at address 0x01043000

INFO : PHY Marvell 88E1116R found at PHY address 0x01 of MAC Group[0]

INFO : PHY[0.0] - Explicitly mapped to tse_mac_device[0]

INFO : PHY[0.0] - Restart Auto-Negotiation, checking PHY link...

INFO : PHY[0.0] - Auto-Negotiation PASSED

INFO : PHY[0.0] - Checking link...

INFO : PHY[0.0] - Link established

INFO : PHY[0.0] - Speed = 1000, Duplex = Full

OK, x=0, CMD_CONFIG=0x00000000

MAC post-initialization: CMD_CONFIG=0x0400020b

[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created

mctest init called

IP address of et1 : 192.168.1.234

DHCP timed out, going back to default IP address(es)

Simple Socket Server starting up

[sss_task] Simple Socket Server listening on port 30

Please folks, I really need to OK this hardware.

Apus

12 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Initialization and console output seem to be ok.

    What did you try so far? Pinging ip address? Trying connection on port 30?

    If ping doesn't work try these preliminary tests:

    - check if ethernet link is up (i.e. NIC link led on or, if you use Windows, ethernet connection notification in the lower right corner of the screen)

    - if your board has an activity led on the eth connector, check if it blinks whenever a ping request is issued

    - check your client tcp/ip configuration (ip address 192.168.1.x with x any from 1 to 254, excluding 234; subnet mask 255.255.255.0)

    - disable dhcp and use a static ip address
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi,

    The system is not transmitting anything on the RGMII lines.

    I can see that the phy is receiving traffic.

    It seems that it is the system itself, so I am going to signaltap the SGDMA's and Nios regs

    Apus
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Ok,

    so it is working now. I had mapped the PHY from addr1 to addr0,

    thinking that it would be a wise thing to do. better leave it to the system.

    But I am now able to connect and transmit data over Gigabit Lan.

    You know, if Altera had specified that we had to setup the TSE during startup instead of stating that the package supports 4 different phy's at default, then it would have saved me a lot of time.

    Anyway, it is cool when it works.

    thanks.

    apus
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I use a different PHY (National DP83640) and mapped it to addr 1 but I haven't had any problem. If I remember correctly in my case it happened the opposite: it didn't work when mapped to addr0, but I had an error message directly in the console output during initialization.

    Regarding the default setup I can tell you this: I have two PHYs on my board and when I configure fpga for using a single TSE and single PHY I don't need to manually setup with the alt_tse_system_add_sys() call.

    I only added it when I started to use the second TSE/PHY channel.

    Cris
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The inner workings of the code is not very clear to me, I only read enough to get the board up and running.

    I am about to start a new layout for a dual phy board.

    Dual gigabit.

    How did that work for you?

    Best regards

    Apus
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I did a minimal debug inside tse driver code and discovered that it can enumerate and setup automatically the devices. If I remember correctly (it was a few months ago...) this works fine as far as you have a single tse. If more than one (like my case was), the successive tse found replaces the previous one in the enumeration list and in the end only the last one was activated. So I had to explicitly call alt_tse_system_add_sys() for both.

    From what I saw inside driver code, if you instead have a single tse with multiple PHYs this doesn't apply.

    Anyway I'm not sure of the inner workings, so it would be better a true Altera expert helps you.

    PS: mine is a 10/100 PHY, not a Gigabit, but I think this doesn't matter.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I only had to learn enough to get the PCB layout approved. I really do not play with Nios anymore, we have other guys that are much more skilled than me.

    Anyway thanks.

    Apus
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi Guys,

    I am really struggling with what seems to be the same problem you experienced. Being a hardware guy with a small amount of software experience ... all I need to do is get the example working on the Altera ep3C120 development board to get approval to use my design. I have pulled my hair out for two weeks, signal tapped and proven that the phy is passing correct packets to the mac ... and seen that the right statistics are being recorded by the MAC. I have never seen the TX LED light up. Actually that may be a lie because I forced the phy into packet generation mode and was capturing packets with wireshark - the tx led may have gone then.

    What exactly do I need to do to get this board simplesocketserver example going?

    I suspect (but lack the reverse softwarer engineering skills to prove) that this might be something to do with the way the phy is addressed...? My thinking is the phy address on this board is 0x12 yet there is only one phy...?

    Any advice would be good ... the addr1 vs addr0 statement confuses me, and I am not really sure where I should set my phy up in the code anyway ... should I add another 88E1111 to the default list as the comments in the code suggest?

    Any advice would be appreciated ... I am going nuts here!
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Hi,

    this is what i did in order to get my single Marvell to work:

    (It's been a while...)

    After that it just worked. I did verify the electronics so i stopped there.

    In alt_iniche_init.c:

    void SSSInitialTask(void *task_data)

    {

    INT8U error_code;

    INT32U x,tmp;

    //Print out the regs to see if it comms with any phy's

    for(x=0;x<0x320/4;x++)

    {

    tmp = IORD(TRIPLE_SPEED_ETHERNET_0_BASE,x);

    printf("Addr: %x, Dta: %x\n",x*4,tmp);

    }

    //Add profile

    alt_tse_phy_profile MV88E1116R = {"Marvell 88E1116R", //

    MV88E1111_OUI, // OUI

    0x24, // Vender Model Number

    0, // Model Revision Number

    0x11, // Location of Status Register

    14, // Location of Speed Status

    13, // Location of Duplex Status

    10, // Location of Link Status

    &marvell_phy_cfg // Function pointer to configure Marvell PHY

    };

    alt_tse_phy_add_profile(&MV88E1116R);

    alt_tse_system_mac sys_mac = {TSE_SYSTEM_MAC(TRIPLE_SPEED_ETHERNET_0)};

    alt_tse_system_sgdma sys_sgdma = {TSE_SYSTEM_SGDMA(SGDMA_ETH_TX, SGDMA_ETH_RX)};

    alt_tse_system_desc_mem sys_mem = {TSE_SYSTEM_DESC_MEM(RAM_DESCRIPTOR)};

    alt_tse_system_shared_fifo sys_sfifo = {TSE_SYSTEM_NO_SHARED_FIFO()};

    alt_tse_system_phy sys_phy = {TSE_SYSTEM_PHY(1, NULL)};

    alt_tse_system_add_sys(&sys_mac, &sys_sgdma, &sys_mem, &sys_sfifo, &sys_phy );

    /*

    * Initialize Altera NicheStack TCP/IP Stack - Nios II Edition specific code.

    * NicheStack is initialized from a task, so that RTOS will have started, and

    * I/O drivers are available. Two tasks are created:

    * "Inet main" task with priority 2

    * "clock tick" task with priority 3

    */

    alt_iniche_init();

    netmain();