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K606's avatar
K606
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3 months ago

Transceiver data corruption

I am trying to externally loopback a simple data-stream using the GTS on the Agilex 5, over an external QSFP loopback module. The GTS is configured as followed: External clock chip: Outputs 156.2...
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Transceiver
K606's avatar
K606
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2 months ago

CheepinC_altera​ furthermore, I have tried using the same design with Quartus 25.3, and also with the all the TX Tap settings listed here

It is still resulting in the same CDR lock issue.

CheepinC_altera's avatar
CheepinC_altera
Icon for Regular Contributor rankRegular Contributor
1 month ago

Hi,

 

Sorry as I might have missed out your latest post notification. 

 

Just would like to check with you if you have had a chance to try with the example design generated by the Direct PHY IP? You can start with the example design, customize and then perform functional simulation to ensure it is meeting your target expectation. After that you can test out in your hardware to check on the behavior. 

 

By the way, as I observed the toolkit screenshots in your previous post, it seems like the TX PLL is not locking as well. Mind further elaborate on this observation?

 

Please let me know if there is any concern. Thank you.

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    20 days ago

    Hi,

     

    Just would like to follow up with you on my previous note. Please let me know if there is any concern. Thank you.