Hi all,I have a design on Quartus 21.3 Pro and I noticed that the External Memory Interface IP for DDR4 memory has some timing violations within the IP core. I would expect that these kind of IP cores have their own timing constraints with their own .sdc files. But it seems that these constraints are not applied when I compiled my design. And I cannot find the generated .sdc file either. Do you know how I can generate that .sdc file and add it into the project by (not sure about this part) Assignments -> Settings -> Timing Analyzer -> ?Thanks in advance

What exact paths are failing? Usually failures in the core for an EMIF would be due to connections to the user logic, not the IP itself which is usually hardened in the I/O (which target device?).

Hi,The failing paths are included in the screenshot attached here. The target device is an Arria 10

The sdc is automatically generated when you "Generate HDL" for the EMIF IP. You can search the .sdc files in the Project Navigator.Or go to Assignment > Setting > Timing Analyzer > SDC Files to include in the project.Quartus should detect and list out all the sdc file in the project.Seems to me the failing path is from EMIF IP to the other part of design. Could you scroll your mouse to the failing path, Right-Click on it, Locate Path (failing path) in the Technology Map Viewer to confirm this is true?Regards,Richard Tan

Hi,In Assignment -> Setting -> Timing Analyzer I see the EMIF ip being added here (the .ip file), but not the generated .sdc file. I think (and hope) Quartus is detecting the generated .sdc and adding it here automatically, even though it doesn't show the generated .sdc files here.For the failing path (I clicked on the one at the top in my previous screenshot), I do see the `tile_ctrl_inst` being highlighted in the Technology Map Viewer.

I don't understand your first paragraph. Does the Quartus able to detect the sdc file? If the sdc is detected and added to the project, then the sdc does get generated. Do you Locate Path and Not Locate Node? Seem to be you Locate Node the From Node. Please confirm. Perhaps you could share your .qar design (Project > Archive Project) so that I can investigate it further.Regards,Richard Tan

Timing constraints of Intel IPs | Altera Community

27 Replies

RichardT_altera
Super Contributor
2 years ago
Here are some example titles for your question, tailored to your situation:
DDR4 EMIF IP Timing Failure on Arria 10
DDR4 EMIF IP Configuration Setting Support on Arria 10
DDR4 EMIF IP Inquiry for Arria 10

You will have a high chance of getting support from the EMIF IP owner.
Choose the one that best fits your specific issue or request.
Once you have your title, you can proceed to file a new case with the relevant details.
Thank you for your cooperation.

Regards,
Richard Tan
- anonimcs
  Contributor
  2 years ago
  Oh, so you mean I have to post another question to the Community, right ? I thought there was another way to ask direct support of the IP owners somehow.
RichardT_altera
Super Contributor
2 years ago
Yes, you need to post another new question. Then an agent will be assigned to your question based on your title first and then description.

Regards,
Richard Tan
RichardT_altera
Super Contributor
2 years ago
Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.
The community users will be able to help you on your follow-up questions.
Thank you and have a great day!
Best Regards,
Richard Tan

Forum Discussion

Timing constraints of Intel IPs

27 Replies

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