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anonimcs's avatar
anonimcs
Icon for Contributor rankContributor
2 years ago

Timing constraints of Intel IPs

Hi all, I have a design on Quartus 21.3 Pro and I noticed that the External Memory Interface IP for DDR4 memory has some timing violations within the IP core. I would expect that these kind of IP co...
Memory
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.

Thank you and have a great day!

Best Regards,

Richard Tan