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anonimcs's avatar
anonimcs
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2 years ago

Timing constraints of Intel IPs

Hi all, I have a design on Quartus 21.3 Pro and I noticed that the External Memory Interface IP for DDR4 memory has some timing violations within the IP core. I would expect that these kind of IP co...
Memory
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

nstead of enabling all pipelines in mm_interconnect_2 at once, could you try to incrementally increase the pipelines one by one to see if it improves?

Also, try using different Compiler Setting Optimization Modes to see if it gets better.

As the slack is getting <0.100, you might want to try running a seed sweep.

I am running different iterations with various settings to see if it can close the timing.


Regards,

Richard Tan


anonimcs's avatar
anonimcs
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2 years ago

I have found a timing fix by tinkering around the Fitter settings, adding the lines below in my .qsf seems to fix timing issues. However, one should not need to try out every single setting out there, there must be another way of fixing the timing for the DDR4 EMIF IP. As you suggested, I already tried incrementing those one by one in addition to adding all of them at once, didn't help..

set_global_assignment -name OPTIMIZATION_MODE "SUPERIOR PERFORMANCE"
...<pin assignments inbetween>
set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 2.0
set_global_assignment -name GLOBAL_PLACEMENT_EFFORT "MAXIMUM EFFORT"