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RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Terasic D8M-FMC Camera Demo written in Verilog But Have No translator for VHDL?

I recently bought a D8M-FMC Camera Module for a Terasic Dev Kit to expand it's capabilities. However all the RTL Demo is written in Verilog. I wrote support at Terasic and they only know how to code in Verilog, they can't convert it to VHDL. I'm only versed in VHDL. I've tried to understand the code but it's a mystery to me.

Is there a online converter from v to vhd ? I've researched but found the only site that converts does not work. I want a verifiable solution and not suggestions.

Video

2 Replies

  • ShengN_altera's avatar
    ShengN_altera
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Hi,


    Actually not necessary to convert verilog to VHDL. You can straight away instantiate the verilog module in VHDL as mixed language.


    Thanks,

    Best Regards,

    Sheng


  • RHobb's avatar
    RHobb
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    That is correct, one can instantiate the verilog module as a prebuilt package and connect the design using the port map feature in VHDL. However I do not wish to use the presets used to build a module in Verilog. I wish to give the community an opportunity to see if there is alternatives, or maybe someone has a translator. The point being I don't want to learn another language to do a one-to-one statement translation to vhdl.