Terasic D8M-FMC Camera Demo written in Verilog But Have No translator for VHDL?

That is correct, one can instantiate the verilog module as a prebuilt package and connect the design using the port map feature in VHDL. However I do not wish to use the presets used to build a module in Verilog. I wish to give the community an opportunity to see if there is alternatives, or maybe someone has a translator. The point being I don't want to learn another language to do a one-to-one statement translation to vhdl.