Forum Discussion
Honored ContributorSynthese failed on DSP-Builder "Out of Memory 4200MB"
Hallo
I'm a student of the univerity o Zurich (Switzerland) and I develop a mp3 encoder/decoder on a Dev Board DE2 Cyclone 2 with EP2C35F672 fpga. The synthese on dsp-builder do not work, I became a errore message "Out of memory 4200 MB". My workstation have x64 OS Windows 7 Prof with 8GB RAM. Can I make settings in DSP-Builder for correct mapping with RAM? Wath for features have the Quartus V9.1 with DSP-Builder V9.1? Does this Version 9.1 work better with RAM-mapping? Thanks you.22 Replies
Altera_Forumit is actually pretty strange seeing out of memory targeting a CII device. i will take a look at your mdl.
- Altera_Forum
i ran your model from the other thread. i changed clock_1.536MHz to clock_1536MHz, and unchecked the specify clock boxes in all of the blocks which used clock_1536MHz just to get it to compile. i was able to successfully run all the way through Signal Compiler's compile, though it did use a ton of RAM.
- Altera_Forum
i am using MATLAB 2008b and Quartus II/DSP Builder 9.1
- Altera_Forum
thank you for try a simulation on your pc.
I have changed my mdl-file, could you test this new file on your pc again? I became the same error "out of memory 4200GB", that's strange... I use Matlab 2009b, quartus 9.0 and dsp-builder 9.0. I have both quartus x32 and x64 on my pc, but is not the OS Win7 x64 that managed the mapping with RAM's? Best regards... - Altera_Forum
I found the failure, I has insert a bus conversation on the output from my IIR with "signed int 16-bit in/out and make settings in DPRAM also signed int 32x16 bit and not inferred.
The reason was, I has to large information with always inferred settings, but is not important at the output from my IIR, when the signal is 205.12584 or only 205. Now the consuption of my RAM are about 1200MB... Thanks... - Altera_Forum
Hi,
I already "Out of memory 4200 MB". But this error is only when I use a parallel adder with 32 inputs. I try to use 31 parallel adder with 2 inputs, but I receive the same error. I try also with Time set Altera Block with 48kHz and 50Mhz at the Output from the Adder. Please could you analyse my circuit? Friday is the presentation... Thanks. - Altera_Forum
in this circuit-version that I upload I try with 31 pipeline adder 2 inputs... the error is the same...
- Altera_Forum
it looks like you go through a very wide demux through pipelined adders to a single output. can you change this to an accumulator that replaces the mux and the adder tree? this should save lots of resources and ease the memory constraints of your design.
- Altera_Forum
how can I make a accumulator with dsp-builder blocks?
- Altera_Forum
just like an accumulator looks. :)
a 2 input adder which feeds into a delay block. the first input of the adder is the same as your demux, and the 2nd comes from the output of the delay block. you can turn on the sclr function in your delay block to clear the accumulator every time you start a cycle. the sclr will be connected to one of the counters (or counter into a comparator) of your design. so clear whenever counter = 0 or 255 or whatever.
