Switch version have some compile errors

Question

Error(18694): The reference clock on PLL "u_gmax2500|u_lvds_dpa_x16|lvds_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll", which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.

之前17.2编译没问题的，现在换成了19.4报这个错误

这个参考时钟输入是来自于另一个PLL的输出

jonway_c_intel · Answer

Hi @FZhao12​  You will need to assign it to a dedicated clock input pin on the same bank. I remember that newer version will block you from using IO pin as clock input to avoid your LVDS SERDES not performing up to specification.Hope this answers your questions.

fzhao12 · Answer

thanks ​There are no other questions for the moment

Forum Discussion

Switch version have some compile errors

2 Replies

Recent Discussions

What Bank Mode of LPDDR5 does Agilex 5 support?

What is source clock of rx_core_clkout of Serial Lite IV IP

Confusion for TX Clock direction for Triple Speed 1G Ethernet IP?

Agilex 5: Connecting multiple AXI Masters to DDR without explicit Interconnect IP

Behavior of 10 GX Avalon-MM Interface for PCI Express* IP Core when byteenable=16'h0000