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FZhao12's avatar
FZhao12
Icon for New Contributor rankNew Contributor
5 years ago

Switch version have some compile errors

Error(18694): The reference clock on PLL "u_gmax2500|u_lvds_dpa_x16|lvds_0|core|arch_inst|internal_pll.pll_inst|altera_lvds_core20_iopll", which feeds an Altera LVDS SERDES IP instance, is not driven...
JonWay_altera's avatar
JonWay_altera
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi @FZhao12​ You will need to assign it to a dedicated clock input pin on the same bank. I remember that newer version will block you from using IO pin as clock input to avoid your LVDS SERDES not performing up to specification.

Hope this answers your questions.