Stratix4GX PCIe development board to used as root port

So you have to build your own motherboard or use a eval card that has a PCIe socket to let another PCIe card connect to your root port.

E.g., look at that board: altera stratix iv gx/gt pci express gen 2 / usb 3.0 / sfp+ development platform (http://www.hitechglobal.com/boards/stratix4gx.htm) from hitech global (http://www.hitechglobal.com).

http://www.hitechglobal.com/images/S4GX-PCIE.jpg

It has a general-purpose connector on top which allows for adapters to be used. One of these is a PCIe plug adapter called »FMC daughter card with x8 PCI Express Root«:

http://www.hitechglobal.com/images/PCIExpress_FMC_f.jpg

Thanks for getting back to me. In my application, I want to use the Altera Stratix4GX as the main rootport. I would like to feed the TLPs to it using Avalon Streaming interface which then is sent out to all other PCIe devices on the motherboard.

So in my application, the block diagram will look like as below:

Processor --> Altera Stratix4gx root port --> Root port on the motherboard --> Reset of the devices on the motherboard.

I notice that the Altera Stratic4gx root port has Base address register, That filters out only specific requests (?)

In my application I need the ability to send out any cycles from processor to the root port on the motherboard via the Stratix4GX Root port. Is that possible? I am bit confused about having BAR in root port which limits this?

Thanks for prompt response.

I would be surprised if you can put a root port on a PCIe expansion card handled by a root port on the motherboard, so the answer is: No, it’s not possible.

As written, the only way to make use of a root port in an FPGA is to drive another end point, or a switch with multiple end points behind it, when connected properly using such a dev kit with a PCIe socket card. Or you can build your own motherboard.

edit:

Maybe you meant something different? You don’t have to be a root port to send out requests on PCIe, but you have to have OS driver support to have proper I/O to I/O communication between your device and another end point. Most of the time it’s easier to let the devices communicate just with the main processor behind the motherboard root complex which then orchestrates data transfers using OS drivers. Only very high I/O rates or low-latency applications require direct device-to-device communication.

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I notice that the Altera Stratic4gx root port has Base address register, That filters out only specific requests (?)

In my application I need the ability to send out any cycles from processor to the root port on the motherboard via the Stratix4GX Root port. Is that possible? I am bit confused about having BAR in root port which limits this?

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I am pretty sure that the root port can send out any requests, but you may have to make use of the most native PCIe application interface like the Avalon ST where you issue all the TLPs natively, instead of an SOPC design.

I’m just developing an end point design with AST interface. I have heard not the best critics about the SOPC adaptors supplied by Altera, so I wanted to make my mistakes myself. I don’t know precisely which BAR decoding you refer to, but I don’t think it’s related to what requests can go out to the PCIe bus/link.

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I would be surprised if you can put a root port on a PCIe expansion card handled by a root port on the motherboard, so the answer is: No, it’s not possible.

As written, the only way to make use of a root port in an FPGA is to drive another end point, or a switch with multiple end points behind it, when connected properly using such a dev kit with a PCIe socket card. Or you can build your own motherboard.

edit:

Maybe you meant something different? You don’t have to be a root port to send out requests on PCIe, but you have to have OS driver support to have proper I/O to I/O communication between your device and another end point. Most of the time it’s easier to let the devices communicate just with the main processor behind the motherboard root complex which then orchestrates data transfers using OS drivers. Only very high I/O rates or low-latency applications require direct device-to-device communication.

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I am not yet clear on why we can not have the following topology if Altera Stratix4GX is truely a root-port. I understand that one may need a logic to convert the processor cycles into Avalon Streaming interface cycles. But that may not be too bad.

Processor --> Stratix4GX Root Port --> Root on Motherboard (Chipset) --> Reste of the Motherboard devices.

I am hoping that in above configuration, the Stratix4GX can pass any requests/completions from processor to Chipset and from chipset to the processor.

When I generated the root port design using megawaizrd flow, it asked about adding BAR in the root port. It seems that the root port allows some memory mapped I/O for itself if this is required but in my application I just need to pass the requests/completions back and forth beween the processor and chipset. I am not sure why is that not possible.

You cannot connect your root port in the Stratix4GX with the root port on the motherboard. There must be only/exactly one root complex in the PCIe fabric, just like in PCI where you can also have just one root complex that drives DEVSEL#, etc. Please refer to PCIe Spec Section 1.3 »PCI Express Fabric Topology«.

Again, it’s not possible the way you want it. You can only drive your own, separate PCIe link as a root port as described above: Design a motherboard with your Stratix4GX as the root port, and it will work.

But I’m still not convinced that a root port is what you really want to instantiate. As an endpoint in a PCIe slot, you can act as a bus master and issue DMA transfers on your own, issued by your CPU. But you cannot be another root port. Period.

I cannot help you for the BAR question as I am not into root port design.

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You cannot connect your root port in the Stratix4GX with the root port on the motherboard. There must be only/exactly one root complex in the PCIe fabric, just like in PCI where you can also have just one root complex that drives DEVSEL#, etc. Please refer to PCIe Spec Section 1.3 »PCI Express Fabric Topology«.

Again, it’s not possible the way you want it. You can only drive your own, separate PCIe link as a root port as described above: Design a motherboard with your Stratix4GX as the root port, and it will work.

But I’m still not convinced that a root port is what you really want to instantiate. As an endpoint in a PCIe slot, you can act as a bus master and issue DMA transfers on your own, issued by your CPU. But you cannot be another root port. Period.

I cannot help you for the BAR question as I am not into root port design.

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From your feedback, I get the impression that the FPGA endpoint can handle this. But I am not sure.

In this scenerio, can the FPGA endpoint start talking to the root-port chipset on power-up (or cold reset)? There may be low level handshake between the root port chipset and the FPGA endpoint - on power up but I am not sure if that enables the FPGA endpoint to start talking like a real processor to the root-port chipset. Basically the PCIe link between the FPGA end-point and the root-port needs to be primary bus. I am not sure if this is possible.

You can’t not use the main processor on the mainboard. You can’t re-route the the root port activity to a processor behind a PCIe link. All PCIe activity is initiated by the operating system on the CPU behind the root complex, and that’s only the main CPU on the base board.

If you really want/need to have a custom processor act as the PCIe root device, you have to build your own motherboard. Especially, if you want to use a standard COTS chipset you have to mimic the matching CPU local bus (or HyperTransport, etc.), but then you don’t need the PCIe root port in the FPGA in the first place.

PCIe is strictly top–down. On top there is the root port, below are end points and switches. No way you can “reverse polarity” on a link and let an end point act as a super-root complex, disabling the main CPU.

Haven’t heard of speedbridge yet. Interesting stuff. here are the docs (http://www.cadence.com/rl/resources/datasheets/sb_express_ds.pdf).

I think you misinterpret its function, though. The device can emulate two different things: (a) a PCIe end point, transparently visible to the PC the speedbridge is plugged into. (b) a PCIe root port when connected to a nice little board (the one with the blue-colored frame) with two sockets, probably connected 1:1, where the second plug is for a PCIe adapter card (e.g. SATA, USB3, 10G Ethernet) you want to test your root port against.

The docs don’t speak – not even suggest – that the speedbridge can act as a root port, connected to a PC’s chipset root port. The specified transparency relates to the use of the drivers running on the PC running the speedbridge card in endpoint mode, emulating the real device function.