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I would be surprised if you can put a root port on a PCIe expansion card handled by a root port on the motherboard, so the answer is: No, it’s not possible.
As written, the only way to make use of a root port in an FPGA is to drive another end point, or a switch with multiple end points behind it, when connected properly using such a dev kit with a PCIe socket card. Or you can build your own motherboard.
edit: Maybe you meant something different? You don’t have to be a root port to send out requests on PCIe, but you have to have OS driver support to have proper I/O to I/O communication between your device and another end point. Most of the time it’s easier to let the devices communicate just with the main processor behind the motherboard root complex which then orchestrates data transfers using OS drivers. Only very high I/O rates or low-latency applications require direct device-to-device communication.
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I am not yet clear on why we can not have the following topology if Altera Stratix4GX is truely a root-port. I understand that one may need a logic to convert the processor cycles into Avalon Streaming interface cycles. But that may not be too bad.
Processor --> Stratix4GX Root Port --> Root on Motherboard (Chipset) --> Reste of the Motherboard devices.
I am hoping that in above configuration, the Stratix4GX can pass any requests/completions from processor to Chipset and from chipset to the processor.
When I generated the root port design using megawaizrd flow, it asked about adding BAR in the root port. It seems that the root port allows some memory mapped I/O for itself if this is required but in my application I just need to pass the requests/completions back and forth beween the processor and chipset. I am not sure why is that not possible.
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