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You cannot connect your root port in the Stratix4GX with the root port on the motherboard. There must be only/exactly one root complex in the PCIe fabric, just like in PCI where you can also have just one root complex that drives DEVSEL#, etc. Please refer to PCIe Spec Section 1.3 »PCI Express Fabric Topology«.
Again, it’s not possible the way you want it. You can only drive your own, separate PCIe link as a root port as described above: Design a motherboard with your Stratix4GX as the root port, and it will work.
But I’m still not convinced that a root port is what you really want to instantiate. As an endpoint in a PCIe slot, you can act as a bus master and issue DMA transfers on your own, issued by your CPU. But you cannot be another root port. Period.
I cannot help you for the BAR question as I am not into root port design.
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From your feedback, I get the impression that the FPGA endpoint can handle this. But I am not sure.
In this scenerio, can the FPGA endpoint start talking to the root-port chipset on power-up (or cold reset)? There may be low level handshake between the root port chipset and the FPGA endpoint - on power up but I am not sure if that enables the FPGA endpoint to start talking like a real processor to the root-port chipset. Basically the PCIe link between the FPGA end-point and the root-port needs to be primary bus. I am not sure if this is possible.
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