Forum Discussion
Altera_Forum
Honored Contributor
15 years agoThanks for your feedback. Yes. I would like to use this for CPU simulation. It seems that PCIe FPGA root port hardIP can not be used. May be Cadence custom designed the pass through bridge that accepts the TLPs from Palladium side and converts into PCIe and viceversa. It may not have its own config space. Cadence speedbridge may have added other layers to meet the PCie spec.
I am not sure if there is a soft IP from FPGA vendor that lets you do similar things.