Stratix4GX PCIe development board to used as root port

In first mode PCIe endpoint mode, I would like to to use the Avalon Streaming interface as a connection to my processor. It seems that in order to do the endpoint emulatin , the speedbridge has to have complete control over the motherboard - including PCI configuration of all devices. The PCIe side of the FPGA connects to the chipset root port on the PC (this technically may be the secondary PCIe link). My processor will send out all the PCIe config cycle over the Avalon streaming interface to configure the motherboard devices. I am not sure if this is possible using the FPGA hard IP. Can the FPGA endpoint pass all the transaction generated on Avalon Streaming TX interface without claiming them? Allso can the root-port chipset support this mode of communication?