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Altera_Forum
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16 years ago

Stratix4 PCIE endpoint Hard IP and Avalon ST

In order to throttle the Avalon ST bus, I am using the Valid signal of the Avalon ST Interface from my application verilog module to PCIe endpoint Hardpoint. In this case, my application module wants...
Altera_Forum's avatar
Altera_Forum
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16 years ago

I see that this is really old, so maybe this has been figured out by now. Just in case...

I think the problem is related to a requirement placed on the valid signal between the sop and eop. The requirement stated in the user guide is that valid must be continuously asserted b/w sop and eop when ready is asserted. So, if you truly have ready=1 all the time, it is not legal to drop the valid anywhere in between your sop=1 and eop=1 cycles. (Refer to tx_st_valid description in Table 5-4 of the PCI Express Compiler User Guide, version 9.1).